- Ph.D., Stanford University, 1980
- M.S., Computer Science and Computer Engineering Stanford University, 1975
- A.B. (with distinction), Computer Science and Comparative Literature, College Scholar program, Cornell University, 1973
Forrest G. Hamrick Professor in Engineering
Associated Faculty in Computer Science
My current research lies at the intersection of cyber security, computer architecture and deep learning. My students and I research how to improve security with deep learning and machine learning, and how to improve the security of deep learning systems. For example, we showed how to detect anomalous behavior in power-grid systems using our enhanced temporal deep learning method. We are also looking at improving smartphone security with machine learning and deep learning.
Another project looks at designing secure open-source processors and caches. We research new design strategies for minimizing timing channels (side channel and covert channel attacks) due to performance optimization features in the microprocessor. We also study the root causes of the recent speculative attacks like Spectre, Meltdown and Foreshadow, and effective defenses against these. I am interested in defining new processor Instruction Set Architecture and microarchitecture, with security built in.
In our past research, we defined secure processor architectures to provide secure enclaves (or TEEs), e.g., the Bastion architecture, before those terms were used in industry products. Our DataSafe architecture showed how to achieve “self-protecting data” that stays secure even when used by untrusted applications. For protection against timing side-channel attacks, we designed several secure cache architectures based on both dynamic partitioning and randomization approaches. These include the Partition-Locked cache, the Random Permutation cache, the Newcache, the Random Fill cache and CATalyst. Some of these break conventional cache design rules that have been taught for decades, yet provide security with minimal performance overhead. We also showed the first practical attack against Last Level Caches (S&P 2015) in Cloud Computing servers, introducing new attack techniques like eviction sets. For cloud computing security, our CloudMonatt architecture showed how to monitor and attest the security health of a cloud customer’s Virtual Machine leased from a cloud provider. We showed how Security-on-Demand could be built into cloud computing in the OpenStack framework. We also showed how to design secure cloud servers where the hypervisor (or Virtual Machine Monitor) may not be trusted in both our NoHype and Hyperwall architectures. We also worked on cryptography acceleration, where some of our novel new instructions, such as advanced Bit Permutation instructions, like the Parallel Extract and the Parallel Deposit instructions, have been implemented in Intel processors, in their Advanced Vector eXtensions (AVX-x) instructions.
I also have extensive industry experience. At Hewlett-Packard, I was a founding architect of the Hewlett Packard Precision Architecture, called PA-RISC or HPPA. For hardware chip design and implementation, I was the lead designer of the first single-chip PA-RISC CMOS microprocessor, and manager of the second. For multimedia, I was chief architect of a cross-functional multimedia architecture team, responsible for the first workstations with multimedia user interfaces rather than just graphical user interfaces. This included real-time video processing in software. I designed the first multimedia instructions for processors, and subsequently, all major processor architectures have added similar multimedia instructions (also called SIMD instructions) to their instruction set architectures.
- Zecheng He, Aswin Raghavan, Sek Chai, Guangyuan Hu and Ruby B. Lee, “Power-Grid Controller Anomaly Detection with Enhanced Temporal Deep Learning”, IEEE Trustcom, August 2019.
- Zhenghong Wang and Ruby B. Lee, "New Cache Designs for Thwarting Software Cache-based Side Channel Attacks", ACM/IEEE International Symposium on Computer Architecture (ISCA), June 2007.
- Fangfei Liu, Hao Wu, Kenneth Mai, and Ruby B. Lee, “Newcache: secure cache architecture thwarting cache side channel attacks”, IEEE Micro 36:5, September 2016.
- Fangfei Liu, Yuval Yarom, Qian Ge, Gernot Heiser and Ruby B. Lee, “Last-Level Cache Side Channel Attacks are Practical”, IEEE Symposium on Security and Privacy (S&P, Oakland), May 2015.
- Champagne, D., Lee, R.B., "Scalable Architectural Support for Trusted Software", IEEE International Symposium on High-Performance Computer Architecture (HPCA), January 2010.
Honors and Awards
- Fellow of the Association of Computing Machinery (ACM), 2001, “for pioneering multimedia instructions in general-purpose processor architecture and innovations in the design and implementation of the instruction set architecture of RISC processors”
- Fellow of the Institute of Electrical and Electronic Engineering (IEEE), 2002, “for contributions to general purpose processor architectures”
- Co-chair of the National Cyber Leap-Year Summit (2009)
- Best Paper Award at International Conference on Information Systems Security and Privacy, 2018.
- Best Paper Award at IEEE Global Communications Conference (Globecomm), 2009.
- Best Paper Award at IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), 2006.
- Best Paper Award at IEEE International Conference on Information Technology (2003).
- Best Paper Award at Design Technology Conference (1986).
- Best Paper Finalist, IEEE International Symposium on High Performance Computer Architecture (2010)
- Best Paper Finalist, International Conference on Information Systems Security and Privacy (2015).
- IBM Faculty award (2008)
- Intel Faculty award (2016, 2006)
- Qualcomm Faculty award (2019)
- Royal Academy of Engineering, UK, Distinguished Visiting Faculty, 2010-2011
- William Mong Distinguished Lecturer, University of HongKong 2015-2016
- Appointed the Forrest G. Hamrick Professor in Engineering, Princeton University, Oct 1998.
- Who’s Who in the World (since 1997), Who’s Who in America, Who’s Who in the West, Who’s Who of American Women.
- Awarded over 130 U.S. and international patents (43 U.S. Patents).