Niraj Jha

Professor of Electrical and Computer Engineering
Director of Graduate Studies
Office Phone
B220 Engineering Quadrangle
  • Ph.D., University of Illinois at Urbana-Champaign, 1985
  • M.S., in Electrical Engineering, State University of New York at StonyBrook, 1982
  • B.Tech., in Electronics & Electrical Communication Engineering, Indian Institute of Technology, Kharagpur, India, 1981

Professor of Electrical and Computer Engineering

I joined the department in 1987 and have been a full professor since 1998. Our research interests include smart healthcare, machine learning, cybersecurity, Internet-of-Things (IoT), energy-efficient computing, and monolithic 3D IC design. Our current research projects are in the areas of:

  • Use of machine learning for smart healthcare
  • Neural network and long short-term memory (LSTM) synthesis for sensor/edge/cloud
  • Energy-efficient inference
  • IoT system security
  • Monolithic 3D IC design: circuits, architectures, applications

The Internet-of-Things (IoT) era promises hundreds of billions of devices or physical objects connected to the Internet.  These objects include sensors, actuators, and processing elements that help us gather data, make intelligent decisions, and optimize processes. IoT is expected to have a potential economic impact of $3-6 trillion per year by 2025, with $1-2.5 trillion of this economic impact (its largest fraction) coming from smart healthcare applications.  These applications will be enabled by wearable medical sensors (WMSs) that will transmit their information to a personal health hub, such as a smartphone or smartwatch.  The sensors and the health hub form a body-area network (BAN). The BAN will communicate with a health server over the Internet, making a complete personal healthcare system possible.  The doctors can communicate with the health server to keep track of an individual’s health. However, many challenges remain in making this vision a reality. Our group is exploring the possibility of diagnosing various diseases in a multi-faceted fashion: (i) using WMSs and machine learning ensembles, (ii) image/video based diagnosis, and (iii) by combining feature and semantic spaces.

Neural networks and LSTMs have begun to have pervasive impact in diverse areas.  However, synthesis of neural networks and LSTMs remains an art.  We are developing methodologies and tools to automatically synthesize them from big/medium/small datasets with the aim of meeting state-of-the-art classification accuracy targets while reducing hardware resources by two-to-three orders of magnitude.

We are also investigating IoT system security from both attack and defense perspectives.  The approach covers the complete IoT spectrum: sensor, edge, and cloud.

Finally, we are interested in monolithic 3D IC design, from devices to systems.  The projects involve design of processor cores, networks-on-chip, SRAMs, memory-processor interfaces, and chip multiprocessors, using a hybrid of various design styles: transistor-level monolithic, gate-level monolithic, and block-level monolithic, and design automation methodologies and tools to support such designs.

I have served as the Editor-in-Chief of IEEE Transactions on VLSI Systems. I am currently serving as an Associate Editor of the Journal of Low Power Electronics. In the past, I have served as an Associate Editor of IEEE Transactions on Circuits and Systems I & II, IEEE Transactions on Computer-Aided Design, IEEE Transactions on Computers, IEEE Transactions on VLSI Systems, IEEE Transactions on Multi-Scale Computing Systems, Journal of Nanotechnology, and the Journal of Electronic Testing: Theory and Applications. I have served as the Program Chairman of the 1992 Workshop on Fault-Tolerant Parallel and Distributed Systems, the 2004 International Conference on Embedded and Ubiquitous Computing, and the 2010 International Conference on VLSI Design. I have also served as the Director of the Center for Embedded System-on-a-Chip Design funded by the New Jersey Commission on Science and Technology, and as the Associate Director of the Andlinger Center for Energy and the Environment.  I have co-authored or co-edited five books: Testing and Reliable Design of CMOS Circuits (Kluwer, 1990), High-Level Power Analysis and Optimization (Kluwer, 1998), Testing of Digital Systems (Cambridge University Press, 2003), Switching and Finite Automata Theory, 3rd ed. (Cambridge University Press, 2009), and Nanoelectronic Circuit Design (Springer, 2010). I have also authored or co-authored 15 book chapters and more than 440 technical papers. 20 of my co-authored papers have won various awards or award nominations. These include a paper selected for “The Best of ICCAD: A collection of the best IEEE International Conference on Computer-Aided Design papers of the past 20 years,” two papers by IEEE Micro Magazine as top picks from the 2005 and 2007 Computer Architecture conferences, and two papers as being among the most influential papers of the last 10 years at the IEEE Design Automation and Test in Europe Conference. I have received 17 U.S. patents.



Selected Publications
  1. X. Dai, H. Yin, and N. K. Jha, "NeST: A neural network synthesis tool based on a grow-and-prune paradigm," accepted for publication in IEEE Trans. on Computers.

  2. X. Dai, P. Zhang, B. Wu, H. Yin, F. Sun, Y. Wang, M. Dukhan, Y. Hu, Y. Wu, Y. Jia, P. Vajda, M. Uyttendaele, and N. K. Jha, "ChamNet: Towards efficient network design through platform-aware model adaptation," IEEE Conf. on Computer Vision and Pattern Recognition, June 2019.

  3. H. Yin and N. K. Jha, "A health decision support system based on wearable medical sensors and machine learning ensembles," IEEE Trans. on Multi-Scale Computing Systems, Oct.-Dec. 2017.

  4. A. O. Akmandor, H. Yin, and N. K. Jha, "Smart, secure, yet energy-efficient, Internet-of-Things sensors," IEEE Trans. on Multi-Scale Computing Systems, Oct.-Dec. 2018.

  5. A. M. Nia and N. K. Jha, "A comprehensive study of security of Internet-of-Things," IEEE Trans. on Emerging Topics in Computing, Sept. 2016.

Google Scholar Profile

Honors and Awards: 

  • Distinguished Alumnus Award, I.I.T., Kharagpur, India (2014)
  • Princeton University Graduate Mentoring Award (2004)
  • ACM Fellow (2003)
  • IEEE Fellow (1998)
  • NEC Preceptorship Award for Research Excellence, School of Engineering & Applied Science, Princeton University (1992)
  • NCR Award for Teaching Excellence, Princeton University (1990)
  • AT&T Foundation Award for Research Excellence (1990)
  • NSF Engineering Initiation Award (1987)
  • 20 Best Paper Awards and Nominations
Research Areas
Biological & Biomedical
Computing & Networking
Data & Information Science
Integrated Circuits & Systems
Robotics & Cyberphysical Systems
Security & Privacy