- Ph.D., Carnegie Mellon University, 1992
- MSECE, Carnegie Mellon University, 1988
- B.S., Providence College and Columbia University, 1984
Jack Kenney received B.S. degrees from both Providence College in Providence, RI and Columbia University New York, NY in 1984 and the MSECE and Ph.D. from Carnegie Mellon University in 1988 and 1992 respectively. Dr. Kenney was on the faculty of the Department of ECE at Oregon State University from 1992 until 1997. He was a Lecturer at Princeton University in 1999 and 2019.
Jack joined Analog Devices Inc. in Somerset, NJ in 1997, and is currently an engineering manager and lead architect in the development of SERDES solutions used on numerous data converter and radio platforms. He supervises a small team of highly skilled engineers who have developed multiple generations of clock and data recovery, deserializers and phase-locked loops in 130nm, 65nmm, 28nm and 16nm FINFet CMOS with data rates up to 11G/12.5G/24.75G/32.5Gb/s.
In addition to his academic and industry experience, Dr. Kenney served on the Wireline Sub-committee for the IEEE International Solid-State Circuits Conference from 2011 until 2015. He was a Guest Editor for the Journal of Solid-State Circuits in 2012 and was an Associate Editor from 2014-2019. His current research interests are high-speed serial I/O design and PLLs especially as they relate to RF data converters.
- J.G. Kenney et al., “A 9.95-11.3 Gb/s XFP Transceiver in 0.13mm CMOS,” IEEE J. of Solid-State Circuits, vol. 41, no. 12, pp. 2901-2910, Dec. 2006.
- W.S. Titus and J.G. Kenney, “A 5.6 GHz to 11.5 GHz DCO for Digital Loop CDRs,” IEEE J. of Solid-State Circuits, vol. 47, no. 5, pp. 1123-1130, Feb. 2012.
- J. Kenney, F. Sabouri, V. Leung, J. Guido, E. Zimany, A. Agrillo, J. Trackim, J. Khoury and R. Shariatdoust, "A 4 Channel Analog Front End for Central Office ADSL Modems," IEEE Custom Integrated Circuits Conference, 2000.