Modern computer systems are increasingly vulnerable to a growing number of attacks, with hardware caches being a critical performance optimization feature and a prime target for exploitation. Traditional cache timing attacks often aim to leak secrets like encryption keys, while recent speculative execution attacks can leak a broader range of sensitive information through cache timing channels.

This dissertation focuses on designing efficient defenses to mitigate these threats. We begin by presenting an analytical framework that characterizes the security guarantees and performance overheads of defenses. Our analysis shows the need for a secure cache to defend against both side-channel and speculative execution attacks.

To address these challenges, we propose the Speculative and Timing Attack Resilient (STAR) cache, designed to counter access-based cache attacks commonly exploited by attackers. We identify potential attacks that could compromise previous randomized caches and enhance the design to mitigate these vulnerabilities. To address speculative execution attacks, we introduce a novel invalidation mechanism that defeats attacks without adding extra work when speculation is correct.

We further propose a novel cache architecture, the Random and Safe (RaS) cache, which changes the predictable fetch and placement policies of traditional caches. RaS prevents cache fills for demand-fetched, security-sensitive lines, instead filling the cache with “safe” lines that are randomly displaced to confuse attackers. RaS defeats the challenging same-domain attacks without changing the set-associative cache architecture. One variant, RaS-Spec, mitigates speculative execution attacks with minimal overhead. Another variant, RaS+, offers security-performance trade-offs to defend against both access-based and operation-based attacks.

Beyond addressing microarchitectural threats, we also investigate methods for detecting anomalous behaviors, such as an unauthorized user (impostor) attempting to access a victim's smartphone. We propose the Smartphone Impostor Detector (SID), a processor architecture that supports a diverse set of attack detection algorithms, in scenarios both with and without other users' data for training. The SID processor provides flexible support for various machine learning, deep learning, and statistical algorithms at minimal cost, making it versatile enough to serve as a general-purpose anomaly detection module.

Adviser:  Ruby Lee