Scalable Deep Neural Network Hardware with Multi-Chip Modules

Nov 17, 2023, 4:30 pm6:00 pm


Event Description

Abstract: Deep neural networks (DNNs) have emerged as a key approach to solving complex problems across many application spaces, including image recognition, natural language processing, robotics, health care, and autonomous driving. Designing custom hardware accelerators for deep neural networks is highly promising, as they offer significant performance and power advantages compared to general-purpose processors. This talk presents a hardware-software co-design framework called MAGNet that takes an application specification as input and produces an ASIC accelerator along with valid mappings for running the target networks. It explores different data formats, quantization techniques, memory hierarchies, and dataflow. A new data format called VS-Quant, which employs a per-vector scaled quantization scheme that employs a two-level scaling scheme for achieving low-precision computation is discussed. It presents novel multi-level dataflows that achieve reuse across different operands to improve energy efficiency.


Bio: Rangharajan Venkatesan is a Senior Research Scientist in the ASIC & VLSI Research group in NVIDIA. He received the B.Tech. degree in Electronics and Communication Engineering from the Indian Institute of Technology, Roorkee in 2009 and the Ph.D. degree in Electrical and Computer Engineering from Purdue University in August 2014. His research interests are in the areas of low-power VLSI design and computer architecture with particular focus in deep learning accelerators, high-level synthesis, and spintronic memories. He has received Best Paper Awards for his work on deep learning accelerators from IEEE/ACM Symposium on Microarchitecture (MICRO) and Journal of Solid-State Circuits (JSSC). His work on spintronic memory design was recognized with the Best Paper Award at the International Symposium on Low Power Electronics and Design (ISLPED), and Best paper nomination at the Design, Automation and Test in Europe (DATE). His paper titled, “MACACO: Modeling and Analysis of Circuits for Approximate Computing”, received the IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Ten Year Retrospective Most Influential Paper Award in 2021. He is a member of the technical program committees of several leading IEEE/ACM conferences including ISSCC, DAC, MICRO, and ISLPED.