Rapidly-increasing demand for high-dimensional data operations, which are the backbone of machine learning, has motivated architectural techniques to address energy and throughput optimization beyond conventional CMOS device scaling. One such approach is in-memory computing (IMC), which leverages the topological characteristics of conventional memory arrays to perform matrix-vector multiples (MVMs), reducing compute costs and amortizing data movement costs. In this talk, I will present the application of in-memory computing to emerging non-volatile memory technologies, namely magnetoresistive RAM (MRAM) and resistive RAM (ReRAM). Non-volatile memory has the advantages of very high density and scaling, low leakage power, low-duty-cycle capability, and harsh-environment robustness. However, device variability and high-conductance states present challenges for high-SNR, area- and energy-efficient IMC readout techniques. I will discuss our series of MRAM demonstration macros, fabricated in 22nm foundry CMOS, and our RRAM demonstration of the same in 40nm CMOS. We achieved superior row-/column-parallelism, energy efficiency and area-normalized throughput, while demonstrating the use of hardware-generalizable stochastic deep neural network training for vision applications, mapped and demonstrated on our test chips.

zoom link: https://princeton.zoom.us/j/98601577093

Adviser: Naveen Verma