In-memory compute with off-the-shelf DRAMs

Pre-FPO Presentation
Feb 3, 2023, 11:00 am12:30 pm
EQUAD B327 & Zoom See abstract for Link



Event Description

In-memory computing has long been promised as a solution to the “Memory Wall” problem. Unfortunately, performing computations with memory resources either has relied on emerging memory technologies which are not readily available today or has required additional circuits be added to RAM arrays.  So far, the competitive and low-margin nature of the RAM industry has made commercial RAM manufacturers resist adding any additional logic into the existing design. In this thesis, we demonstrate methods of in-memory compute with off-the-shelf DRAM chips without any hardware modification, thus make it more realistic and ready-to-use.

We found that specially timed DRAM command sequences lead to undocumented, but also constructive and stable, behaviors in DRAM array. We studied and characterized those behaviors with a customized DRAM controller and unmodified DRAM modules from multiple vendors. The first work, ComputeDRAM, proposes DRAM command sequences that can open multiple DRAM rows at the same time, thereby enabling bit-line charge sharing. With the charge sharing, we implement intra-subarray row copy and majority-of-three operations. Subsequently, we employ these primitive operations to develop an architecture for arbitrary, massively-parallel, computation with off-the-shelf DRAM. The second work, FracDRAM, proposes command sequences to set the DRAM cell voltage level with fine control, so that fractional values can be stored in a single cell. Utilizing fractional value storage, this work enables more modules to perform the in-memory majority operation, increases the stability of the existing in-memory majority operation, and builds a state-of-the-art DRAM-based PUF with unmodified DRAM. 


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