In-memory Computing (IMC) is an emerging approach to address the compute and data-movement costs in high-dimensional matrix-vector multiplies (MVM), a major operation in deep learning. However, IMC suffers from a range of noise sources, including analog and quantization noise, which cannot be avoided in practical hardware. In this talk, I will discuss approaches to enable deep learning applications for IMC systems in the presence of such noise, across different IMC technologies.
I will start by discussing methods to overcome the effects of analog noise. The first work, Stochastic Data-Driven Hardware Resilience (SDDHR), primarily addresses process variations, which is the dominant analog noise in advanced node silicon technologies. This approach constructs a stochastic model of the hardware, represents variation statistics during the training period, and enables the inference system to achieve high performance with the hardware variation present. However, it is found that this approach is not sufficient to fully recover the performance degradation in practical energy- and density-aggressive IMC chips. Our second work proposes a holistic framework, including a contrastive and progressive training algorithm to further enhance the model robustness to hardware noise, and an MVM level modelling approach abstracted from circuit-level noise, whose parameters can be calibrated from a small number of hardware measurements. Recently, SRAM-based IMC employing switched capacitor analog operation has become promising due to its robustness and scalability. But, it suffers from the extra quantization noise introduced by ADC hardware. While neural network quantization for activations and weights has been well studied, ADC quantization has not been investigated in detail. Our next work proposes training algorithms along with a novel number representation to make the network aware of the presence of ADC quantization.
Adviser: Naveen Verma