Energy-efficient and high-SNR SRAM in-memory computing (IMC) macros with mixed signal computation

Jun 30, 2023, 10:00 am11:00 am
EQUAD J323 & Zoom (See abstract for link)



Event Description

In recent years, in-memory computing (IMC) has gained widespread recognition for its high-performance capabilities in matrix-vector multiplications (MVMs). However, among the analog computing methods used in IMC macros, current-based IMC has faced challenges with non-linearity and poor signal-to-noise ratio (SNR) performance. This presentation focuses on charge-based IMC macros that employs mixed-signal computation to overcome these limitations.

The first part of the talk introduces a row/column-parallel IMC macro with a dynamic range doubling method for the input activation driver. The utilization of parallelism in both the row (input) and column (weight) dimensions empowers the macro to efficiently execute complex machine learning models, including neural networks, while simultaneously enhancing throughput performance. A novel dynamic range doubling technique is employed to improve circuit complexity, energy efficiency, and compensation against parasitics. The results showcase state-of-the-art energy efficiency and include a successful demonstration on the CIFAR-10 dataset.

Next, an IMC macro design featuring reconfigurable input and weight bits is presented. This reconfigurability further amortizes the energy consumption of the read-out circuit, surpassing the energy efficiency achieved by the previous chip.

Lastly, an IMC macro design incorporating 2b-bitcell and differential charge accumulation is proposed. As the dynamic range requirements of MVMs become larger due to the intricacy of neural network models, it is important for IMC macros to quantize MVM outputs with minimal errors. The novel design, involving differential charge accumulation across rows and utilizing 2b-bitcell technology, enhances SNR while staying within the resource budget.

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Adviser: Naveen Verma