As Moore's Law approaches its limits, the quest for increased transistor density in silicon chips encounters new challenges. Computer architects are increasingly turning to multi-chiplet designs, partitioning logic across multiple dies within a single package. These multi-chiplet architectures bring forth fresh challenges, such as heightened simulation complexity and increased inter-core latencies. Simultaneously, they open doors to exciting possibilities, including heterogeneous integration and high-bandwidth on-package interconnects.

This dissertation delves into an exploration of these challenges and opportunities. First, it highlights the critical role of on-package interconnect scaling as a valuable resource to enhance the performance of multi-chiplet systems. Specifically, we demonstrate the efficacy of adapting bandwidth-demanding write-update coherence protocols to modern multi-chiplet systems, significantly boosting their performance. Second, we address the issues associated with modeling multi-chiplet architectures in contemporary software simulators. We introduce SMAPPIC, a novel prototyping platform for large multi-chiplet systems that leverages a Cloud multi-FPGA setup to enable fast, scalable, accurate, and cost-effective multi-chiplet modeling. We detail the platform's design and showcase numerous use cases empowered by SMAPPIC. Finally, we explore the future prospects of multi-chiplet systems, shedding light on the potential advancements and innovations in this evolving landscape.

Adviser: David Wentzlaff

Zoom Metting: https://princeton.zoom.us/j/91664264604