Benchmarking digital logic styles for high-performance OTFT circuits

Mar 31, 2023, 10:00 am11:30 am



Event Description

Organic thin-film transistors (OTFTs) have experienced substantial growth in usage in the past three decades. Unlike silicon(Si) circuits, in which complementary logic is the mainstream circuit style, the choice of logic style for organic semiconductors varies. Thus, benchmarking various logic styles is an important step for circuit optimization and application viability.

In this thesis, we focus on designing and benchmarking different logic styles for OTFT circuits.  In the first part(chapters 1 to 3), we start with the motivation for using organic semiconductors for sustainable electronics, introducing the fundamentals of organic semiconductors and the operation of organic thin film transistors. We discuss the design and fabrication of an individual OTFT, based on pentacene (for p-type) and C60 (for n-type). A bottom-gate, top-contact structure is implemented. A level-61 spice model is designed to simulate the static and dynamic behaviors of the transistor. We also discuss the main optimization for the fabrication process, including shadow mask alignment, surface plasma treatment, and encapsulation technique.

In the second part of the thesis (chapters 4 and 5), we design and evaluate different types of static and dynamic logic OTFT circuits. For static logic, we start from the characterization of a simple complementary inverter and a NAND gate, analyzing the impact of sizing and operating frequency. Then we characterize various types of p-type only circuits, analyzing the impact of circuit structure and bias-voltage, concluding that pseudo-E logic has the best performance for p-type only static logic. For dynamic logic, we measured the performance of complementary pre-charge, complementary pre-discharge, and p-type only pre-discharge circuits, analyzing their functionality based on static inputs, and comparing the dynamic performance based on dynamic inputs.

Finally, we benchmark the performance of static/dynamic circuits. Overall, we expect that complementary static logic should be implemented for large-scale system designs, with p-type only pre-discharge dynamic logic providing an alternative technology for applications concerned with area and power consumption. P-type only pseudo-E static logic may also be used as an alternative technology with better post-fabrication tunability and simpler fabrication process flow.


Co-Advisers: Barry Rand and David Wentzlaff