The slowdown of Moore's law has triggered researchers to propose novel computer architectures either to maintain the performance gain or to expand to exciting application spaces. This thesis is two-pronged, first focusing on designing the architecture for future biodegradable computing with organic technology, then discussing how to efficiently supply data for different data layout requirements posed by gradually more heterogeneous architectures.
Organic thin-film transistors (OTFTs) have attracted increased attention due to the possibility of producing environmentally friendly, low-cost, lightweight, flexible, and even biodegradable devices. With an increasing number of complex applications being proposed for organic and biodegradable semiconductors, the need for both expediting the design process and increasing computation horsepower rises. However, due to the process characteristic differences, direct adaptation of silicon-based circuit designs and traditional computer architecture wisdom is not directly applicable.
This thesis first proposes a commercial tool compatible, RTL-to-GDS flow along with a standard cell library based on bottom gate, top contact, pentacene OTFTs, and creates an organic process design kit (PDK) developed based on the developed process. This organic design flow is demonstrated by fabricating and evaluating the generated layout of the digital designs.
This thesis then presents on architectural design space exploration for processor cores made with the organic semiconductor process using the standard cell library built with experimentally validated data. This thesis builds an OTFT simulation framework based on experimental pentacene OTFTs. Our results demonstrate that, compared to modern silicon, organic semiconductors favor building deeper pipelines and wider superscalar designs.
As the end of Moore's law approaches, in addition to expanding the use case of electronics by investigating emerging technologies, computer system designers have turned to more domain-specific and heterogeneous architectures and supplying data efficiently and intelligently to utilize the full potential of computing capabilities has become a focal issue that needs to be resolved.
This thesis explores the opportunities of supplying heterogeneous computing components with data optimized for their memory access patterns. A data layout transformation engine, which is integrated and taped-out with a tile-based heterogeneous architecture, is designed based on the observations made by analyzing tradeoffs between different data layouts.